1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, particularly to a structure of a semiconductor integrated circuit device incorporating a tester circuit to test a semiconductor memory device.
2. Description of the Background Art
Most semiconductor memory devices have a spare memory cell. When there is a defective memory cell in the memory cells, that defective portion can be replaced with the spare memory cell to repair a defective chip.
FIG. 39 is a schematic block diagram showing a structure of a redundant circuit provided for a memory array unit 8010 of such a semiconductor memory device.
One memory cell in memory array unit 8010 is selected by externally applied row address signals RA0-13 and column address signals CA0-8. In a write operation, the data applied to a data input/output terminal DQ (not shown) is written into the selected memory cell. In a readout operation, the data read out from memory array unit 8010 is provided to data input/output terminal DQ.
A row decoder 8020 responds to the input row address to select memory cells of one row for a read or write operation. A column decoder 8030 selects one column according to the input column address and further selects one memory cell out of the one row of memory cells selected according to the row address.
Detection of a defective memory cell and analysis to replace that defective memory cell by a redundant memory cell array is generally carried out by an external memory tester of a semiconductor memory device 8000.
In these few years, a semiconductor memory device including the so-called built-in test device that has a signal generator provided in a semiconductor device with a semiconductor memory device to carry out testing without a memory tester, or a semiconductor device incorporating a semiconductor memory device with such a built-in test device are produced.
In such a semiconductor memory device or semiconductor device incorporating such a built-in test device, it is difficult to carry out testing realizing a redundancy analysis function itself even if the testing of whether there is a defective memory cell or not in the memory cell can be carried out. The failure memory to store the address of the defective memory cell requires a capacity equal to that of the semiconductor memory device to be tested or the semiconductor memory device incorporated in the semiconductor device. In practice, it is difficult to incorporate a failure memory of such a capacity in a semiconductor memory device or a semiconductor device. Therefore, redundancy analysis could not be carried out.
A trend is towards increased data bit width for the data input/output of a semiconductor memory device from the standpoint of speeding the system. Accordingly, the memory cell array is divided into sub memory cell arrays, wherein a plurality of memory cells are selected simultaneously for each sub memory cell array. Therefore, the aforementioned redundancy analysis becomes more complicated.